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Search - SATH: Simulated Annealing C code To FPGA Hardware compiler: Customizing Pipelined Simulated Annealing IP cores with a dedicated C to FPGA compiler

SATH: Simulated Annealing C code To FPGA Hardware compiler: Customizing Pipelined Simulated Annealing IP cores with a dedicated C to FPGA compiler
SATH Simulated Annealing C code To FPGA Hardware compiler Customizing Pipelined Simulated Annealing IP cores with a dedicated C to FPGA compiler
Author: Jonathan Phillips
A tool flow is presented for deriving accelerator circuits on an FPGA from ANSI C source code by exploring architecture solutions that conform to a preset template through scheduling and mapping algorithms. A case study carried out on simulated annealing-based scheduling software used for spacecraft systems is explained. The goal ...  more »
ISBN-13: 9783639165128
ISBN-10: 3639165128
Publication Date: 7/8/2009
Pages: 132
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Publisher: VDM Verlag
Book Type: Paperback
Members Wishing: 0
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