Skip to main content
PBS logo
 
 

Search - Verification Methodology Manual for SystemVerilog

Verification Methodology Manual for SystemVerilog
Verification Methodology Manual for SystemVerilog
Author: Janick Bergeron, Eduard Cerny, Alan Hunter, Andy Nightingale
Functional verification remains one of the single biggest challenges in the development of complex system-on-chip (SoC) devices. Despite the introduction of successive new technologies, the gap between design capability and verification confidence continues to widen. The biggest problem is that these diverse new technologies have led to a prolif...  more »
ISBN-13: 9780387255385
ISBN-10: 0387255389
Publication Date: 9/28/2005
Pages: 510
Edition: 1
Rating:
  ?
0 stars, based on 0 rating
Publisher: Springer
Book Type: Hardcover
Members Wishing: 0
Reviews: Amazon | Write a Review


Genres:


Back to the Top ↑
By using this Web site, you confirm that you have read, understood, and agreed to be bound by the Terms of Use. As an Amazon Associate we earn from qualifying purchases.
US Patent Number 7,877,315 | Copyright © 2004 - 2024 PaperBackSwap.com. All Rights Reserved.