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The Power of Assertions in SystemVerilog
The Power of Assertions in SystemVerilog
Author: Eduard Cerny, Surrendra Dudani, John Havlicek, Dmitry Korchemny
This book provides a deeper understanding of the meaning of the enhancements contained in the new SystemVerilog 1800-2009 LRM. In particular, it discusses the context of practical deployment in hardware design projects. The material also addresses language implementation alternatives and their impact on simulation performance as well as the abil...  more »
ISBN-13: 9781441965998
ISBN-10: 1441965998
Publication Date: 10/22/2010
Pages: 561
Edition: 1st Edition.
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Publisher: Springer
Book Type: Hardcover
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