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Writing Testbenches using SystemVerilog
Writing Testbenches using SystemVerilog
Author: Janick Bergeron
Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology. Writing Testbenches Using SystemVerilog offers a clear bluepr...  more »
ISBN-13: 9780387292212
ISBN-10: 0387292217
Publication Date: 2/10/2006
Pages: 414
Edition: 1
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Publisher: Springer
Book Type: Hardcover
Members Wishing: 0
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